Unless otherwise indicated herein, the materials described herein are not prior art to the claims in the present application and are not admitted to be prior art by inclusion in this section.
Active heat loads such as active integrated circuits (ICs) may be mounted on top of heat sinks on a printed circuit board (PCB) and may generate heat during operation. Inefficient heat removal from the active loads may affect the performance of the active loads and/or the PCB. For example, in high-frequency applications (e.g., ≥25 gigabits per second), performance of the active loads and/or PCB may be degraded significantly if the heat is not removed efficiently. Existing technologies may rely on thermal vias to remove the heat in the z direction (e.g., orthogonal to the plane of the PCB). The vias are hollow holes filled with thermal conductive materials such as copper and may take up a substantial portion of space on the PCB. The vias may create bumps under the active loads and may also cause flatness issues. Signal routing on the PCB may be affected by the distribution of the vias on the PCB. Alternatively or additionally, existing technologies may use coining to create local thermal pools directly underneath the active loads and to remove the heat from the active loads. Coining may also interfere with signal paths on the PCB.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one exemplary technology area where some embodiments described herein may be practiced.